1. Field of the Invention
The present invention relates to a device for the conversion of a series signal received in the form of a low-amplitude, high-frequency differential signal into a number, n, of parallel signals. The invention can be applied more particularly in the field of serial data reception.
The use of a differential signal is particularly suited to the transmission of data elements in series links. Disturbances, such as distortions and noise, that appear during the transmission of the signal act without distinction on the two signals that form the differential signal, and therefore do not cause any deterioration in the information to be transmitted which constitutes the difference between the two signals.
The conversion device as described in the present application is used to convert a high-frequency and low-amplitude differential signal representing a string of bits into n parallel logic signals.
2. Description of the Prior Art
Known conversion devices generally have a differential input to receive a series differential signal with a period T. This signal is applied to the inputs of a differential amplifier so as to transpose it to two logic levels Vdd and Vss. The converted signal is then sampled by a set of n master/slave registers which are parallel-connected to the output of the amplifier. The sampling period of the registers is taken to be equal to nT and the sampling signals of the n master/slave registers are staggered with respect to one another by a time interval equal to the period T of the differential signal. Thus, at the output of the n master/slave registers, there are obtained n samples of the series signal staggered by a time interval T.
For example, for the conversion of a string of bits received at a frequency of 100 KHz in 10-bit words, the conversion device has ten master/slave registers that sample the string of bits at a frequency of 10 KHz and the sampling instants of these different registers are staggered by 10 .mu.s with respect to each other.
However, this type of device does not work satisfactorily when the frequency of the string of bits received is high, in the range of one gigahertz. At this frequency, the differential amplifier introduces an instability in the time base of the signal received and therefore shifts the edges of the series signal. This phenomenon is accentuated when the differential signal applied to the input of the amplifier contains noise in common mode. The result is that the samples obtained at the output of the master/slave registers may, in certain cases, no longer represent the initial string of bits.